Pipelined implementations of the a Priori Error-Feedback LSL algorithm using logarithmic arithmetic

In this paper we present several implementations of the Modified A Priori Error-Feedback LSL (EF-LSL) algorithm [1] on the VIRTEX FPGA. Its computational parallelism and pipelinabilty are important advantages. Internally, the computations are based on the logarithmic number system. We compare 32-bit (SINGLE-ALU or DUAL-ALU version) and 20-bit (QUADRI-ALU versions). We show that the LNS implementation can outperform the standard DSP solutions based on 32-bit floating-point processors.