On-chip debug architecture for MCU-DSP Core based system-on-chip

The migration from system on printed circuit boards (PCBs) to system-on-chips (SoCs) has moved more and more components onto SoCs. An unintended side effect of this higher integration level is the decreasing system observability and controllability, and consequently resulting in novel debug challenges for embedded system development [1]. This paper presents an on-chip debug architecture that can help conquer the challenges. The on-chip debug architecture is integrated into the 32-bit static superscalar MCU-DSP Core based SoC and includes three main components: the JTAG Controller, the On-chip Debug Module and the Core Debug Module. This modular architecture can support the following typical debug features with low hardware overhead: real-time run control, access internal registers and local memory on the fly, complex hardware breakpoints and single-stepping.