DocumentCode
547623
Title
A duty cycle corrector based frequency multiplier
Author
Navidi, M.M. ; Abrishamifar, A.
Author_Institution
Iran University of Science and Technology
fYear
2011
fDate
17-19 May 2011
Firstpage
1
Lastpage
4
Abstract
In this paper a modified frequency multiplier based on a low power duty cycle corrector is presented. The proposed circuit multiplies the output frequency of a PLL, by 3. Also, the output duty cycle of the multiplier could be controlled by changing the ratio of charging/discharging current of the charge pump. This circuit is simulated by using 0 18 um CMOS process. When the VCO operates at 846MHz the power dissipation of the circuit is 1.16mW at 1.8V supply voltage.
Keywords
Charge pumps; Clocks; Frequency control; Phase locked loops; Ring oscillators; Time frequency analysis; Voltage-controlled oscillators; Duty Cycle Correction; Frequency multiplier; Voltage Controlled Oscillator;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Engineering (ICEE), 2011 19th Iranian Conference on
Conference_Location
Tehran, Iran
Print_ISBN
978-1-4577-0730-8
Electronic_ISBN
978-964-463-428-4
Type
conf
Filename
5955511
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