A 10-Bit 100-MSample/s pipelined analog-to-digital converter using digital calibration technique

This paper presents a 10-bit 100-Msample/s pipelined analog-to-digital converter (ADC) using the foreground mode of calibration technique proposed in [1]. This technique can overcome the capacitors mismatch, gain error, and amplifier nonlinearities. Simulation results show that the ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 64 dB, a peak spurious-free dynamic range (SFDR) of 74 dB, a differential nonlinearity (DNL) of 0.12 least significant bit (LSB) and a integral nonlinearity (INL) of 0.3 LSB for a sinusoidal input signal with 30 MHz frequency. The ADC core (without calibration circuitry) consumes 27mW power from a 1V supply voltage in a 90-nm CMOS technology.