Activity aware clock gated storage element design

In advanced sub-nanometer technologies, along with area and timing, power consumption is the major concern. Dynamic power is mostly the dominant component of total power consumption, and clock subsystem of a digital circuit has a large share in the dynamic power consumption which is mostly due to its high toggling rate and large capacitive loading. A new clock gating methodology for low-power clocked storage element design is presented. The proposed method removes unnecessary clock toggling and reduces capacitive loading, which both lead to reduced dynamic power and reduced design complexity. The proposed method is an ad-hoc method and does not require access to internal circuitry of storage element, which makes it feasible in the standard-cell based digital circuit design. The HSPICE simulation results conducted in 45nm CMOS technology confirm more than 20% less power consumption at low activity rate, and higher activity-rate crossover point compared to ordinary clock gating methods.