A 10-Bit 100-Msample/s pipelined analog-to-digital converter using digital calibration technique

Summary from only given. This paper presents a 10-bit 100-Msample/s pipelined analog-to-digital converter (ADC) using foreground mode of calibration technique proposed in [1]. This technique can overcome capacitor mismatches, gain error, and amplifier nonlinearities. With a 30 MHz sinusoidal input signal, simulation results show that the pipelined ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 64 dB, a peak spurious-free dynamic range (SFDR) of 74 dB, a differential nonlinearity (DNL) of 0.12 least significant bit (LSB) and a integral nonlinearity (INL) of 0.3 LSB. The core of ADC (without calibration circuitry) consumes 27mW from 1V supply voltage in 90-nm CMOS.