A method to leverage pre-silicon collateral and analysis for post-silicon testing and validation

Post-silicon testing and validation - whether to screen out defective parts, confirm proper operation in the target application, or test robustness in the presence of transient issues induced by environmental factors - is especially crucial for safety-critical devices. These activities sometimes leverage information gathered prior to fabrication through the injection and testing of stuck-at and transient faults. Traditionally, this process requires a gate-level model in which faulty logic nodes are modeled as 0 and 1 either statically or dynamically. Operating on this unfamiliar gate-level model is a laborious task for engineering teams, requiring a significant investment in time and compute power. This complicates the tasks of better equipping designs for safety-critical needs and augmenting production test quality metrics using well-chosen functional tests. This paper presents research into new techniques for speeding up this process using RTL models and RTL simulation.