Novel tellurium co-implantation and segregation for effective source/drain contact resistance reduction and gate work function modulation in n-FinFETs

Author

Koh, Shao-Ming ; Ding, Yinjie ; Guo, Cheng ; Leong, Kam-Chew ; Samudra, Ganesh S. ; Yeo, Yee-Chia

Author_Institution

Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore (NUS), Singapore, Singapore

fYear

2011

fDate

14-16 June 2011

Firstpage

86

Lastpage

87

Abstract

We report the demonstration of a new contact resistance reduction technology for n⁺ Si S/D using Tellurium (Te) implant and segregation, achieving a low electron SBH of 0.11 eV. The Te implant reduced contact resistance in n-FinFETs by 40 %. When integrated in a process flow where Te is also introduced into the gate, improvement in gate electrostatic control is observed, leading to an improvement in ballistic efficiency. At I_Off of 100 nA/μm, Te implant increases I_On by 22 % as compared with control FinFETs without Te implant.

Keywords

MOSFET; contact resistance; elemental semiconductors; silicon; tellurium; Si; Te; ballistic efficiency; electron SBH; electron volt energy 0.11 eV; gate electrostatic control; gate work function modulation; n-FinFET; process flow; source-drain contact resistance reduction; tellurium coimplantation; tellurium segregation; Annealing; Electrostatics; FinFETs; Implants; Logic gates; Silicon; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSIT), 2011 Symposium on

Conference_Location

Honolulu, HI

ISSN

0743-1562

Print_ISBN

978-1-4244-9949-6

Type

conf

Filename

5984652