Circuit techniques to improve disturb and write margin degraded by MOSFET variability in high-density SRAM cells

Author

Yabe, T. ; Kawasumi, A. ; Hirabayashi, O. ; Kushida, K. ; Suzuki, A. ; Takeyama, Y. ; Tachibana, F. ; Fujimura, Y. ; Niki, Y. ; Shizuno, M. ; Sasaki, S.

Author_Institution

Semicond. Co., Toshiba Corp., Kawasaki, Japan

fYear

2011

fDate

14-16 June 2011

Firstpage

106

Lastpage

107

Abstract

Device variability caused by continued technology scaling makes degradation of disturb and write margin a serious problem for SRAM cells. This paper reports the circuit techniques to cope with it, focusing on two topics: (1) Level Programmable Wordline Driver (LPWD) with Dynamic Array Supply Control (DASC) and (2) Constant-Negative Level Write Buffer (CNL-WB).

Keywords

MOSFET; SRAM chips; CNL-WB; DASC; LPWD; MOSFET variability; circuit techniques; constant-negative level write buffer; device variability; disturb-and-write margin degradation; dynamic array supply control; high-density SRAM cells; level programmable wordline driver; technology scaling; Arrays; CMOS integrated circuits; Degradation; MOS devices; Power supplies; Random access memory; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSIT), 2011 Symposium on

Conference_Location

Honolulu, HI

ISSN

0743-1562

Print_ISBN

978-1-4244-9949-6

Type

conf

Filename

5984662

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=549719