Towards 1X DRAM: Improved leakage 0.4 nm EOT STO-based MIMcap and explanation of leakage reduction mechanism showing further potential

We establish a new record low leakage (J_G)-EOT for DRAM compatible MIMcap by further J_G reduction to 2×10^-8 (10^-7) A/cm² at 0.45 (0.40) nm EOT (0.8 V) using an improved RuO_x/TiO_x/Sr-rich Sr_xTi_yO_z (STO) stack. Further, for the first time we provide insight explaining the origin of the record low J_G-EOT achieved, by detailed studies of our TiO_x/STO stack on TiN, Ru and RuO_x bottom electrodes (BE). TiO_x reduces EOT on all BE (without degrading microstructure), but RuO_x is needed for low J_G. We prove the latter is NOT due to a work function (WF) effect, measuring -on the contrary- strong Fermi Level Pinning (FLP) at STO midgap and same e-injection barrier (~1.6 eV) from TiN, Ru or RuO_x. We determine leakage is controlled by similar traps (~0.8 eV below CBE) in STO for all stacks and BE, and attribute improvement with RuO_x to local STO trap density reduction by eliminating (or even reversing) oxygen scavenging effects near the electrode during crystallization. We demonstrate the potential for further J_G reduction by lowering trap density, with theoretical limit for trap-free STO of 10^-15 A/cm² at EOT~0.4 nm. These results make STO a clear candidate for future DRAM.