• DocumentCode
    549798
  • Title

    In-substrate-bitline sense amplifier with array-noise-gating scheme for low-noise 4F2 DRAM array operable at 10-fF cell capacitance

  • Author

    Yanagawa, Y. ; Sekiguchi, T. ; Kotabe, A. ; Ono, K. ; Takemura, R.

  • Author_Institution
    Central Res. Lab., Hitachi, Ltd., Tokyo, Japan
  • fYear
    2011
  • fDate
    15-17 June 2011
  • Firstpage
    230
  • Lastpage
    231
  • Abstract
    An in-substrate-bitline sense amplifier (SA) with an array-noise-gating (ANG) scheme - for stable sensing operation in a 4F2 DRAM array with cell capacitance of under 20 fF - is proposed. A circuit simulation assuming 40-nm-class 4F2 DRAM chip shows that the SA reduces noise by 58% compared to a conventional SA and achieves stable sensing operation even at cell capacitance of 10 fF.
  • Keywords
    DRAM chips; amplifiers; circuit noise; circuit simulation; In; array-noise-gating; capacitance 10 fF; cell capacitance; circuit simulation; indium-substrate-bitline sense amplifier; low-noise 4F2 DRAM array; size 40 nm; Arrays; Capacitance; Microprocessors; NIST; Noise; Sensors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits (VLSIC), 2011 Symposium on
  • Conference_Location
    Honolulu, HI
  • ISSN
    2158-5601
  • Print_ISBN
    978-1-61284-175-5
  • Type

    conf

  • Filename
    5986050
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=549798