A 27% active-power-reduced 40-nm CMOS multimedia SoC with adaptive voltage scaling using distributed universal delay lines

Author

Ikenaga, Yoshifumi ; Nomura, Masahiro ; Suenaga, Shuji ; Sonohara, Hideo ; Horikoshi, Yoshitaka ; Saito, Toshiyuki ; Ohdaira, Yukio ; Nishio, Youichirou ; Iwashita, Tomohiro ; Satou, Miyuki ; Nishida, Koji ; Nose, Koichi ; Noguchi, Koichiro ; Hayashi, Yos

Author_Institution

Renesas Electron. Corp., Kawasaki, Japan

fYear

2011

fDate

15-17 June 2011

Firstpage

186

Lastpage

187

Abstract

AVS technique for extremely scaled SoCs has been developed. To reduce design cost, we have developed a supply voltage control scheme employing universal delay line (UDL), rather than a replica delay line, for monitoring the critical path delay (T_CRIT). The UDL can be used in any product without any need for customizing. The error to T_CRIT is as small as that with replica delay line. We have shown that 40-nm CMOS SoCs using our AVS can reduce active power by 27%.

Keywords

CMOS integrated circuits; power aware computing; system-on-chip; voltage control; AVS technique; active-power-reduced CMOS multimedia SoC; adaptive voltage scaling; critical path delay; design cost reduction; distributed universal delay line; size 40 nm; supply voltage control; Delay; Delay lines; Logic gates; Monitoring; System-on-a-chip; Voltage control; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSIC), 2011 Symposium on

Conference_Location

Honolulu, HI

ISSN

2158-5601

Print_ISBN

978-1-61284-175-5

Type

conf

Filename

5986097