DocumentCode
549892
Title
Comprehensive SRAM design methodology for RTN reliability
Author
Takeuchi, Kiyoshi ; Nagumo, Toshiharu ; Hase, Takashi
Author_Institution
Renesas Electron. Corp., Sagamihara, Japan
fYear
2011
fDate
15-17 June 2011
Firstpage
130
Lastpage
131
Abstract
In this paper, a comprehensive design flow for achieving reliable SRAMs against random telegraph noise (RTN) is presented. The tailing information of RTN amplitude distributions is important for guardbanding, and can be directly extracted from SRAM test results. Monte Carlo simulation is in excellent agreement with the measurements, and can be used for detailed design. A simple extrapolation method for intuitive understanding of long term RTN impact is also proposed.
Keywords
Monte Carlo methods; SRAM chips; circuit noise; circuit reliability; extrapolation; network synthesis; Monte Carlo simulation; SRAM design; design flow; extrapolation method; random telegraph noise amplitude distributions; reliability; Extrapolation; Life estimation; Noise; Random access memory; Reliability; Transistors; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits (VLSIC), 2011 Symposium on
Conference_Location
Honolulu, HI
ISSN
2158-5601
Print_ISBN
978-1-61284-175-5
Type
conf
Filename
5986434
Link To Document