Design and implementation of an FPGA-based high-performance improved vector-reduction method

Vector-reduction operation is the basis of many scientific computations. FPGA-based vector-reduction circuit must use deeply pipelined floating-point IP cores to gain a performance advantage over general-purpose processor (GPP). Improper design of reduction circuit will destroy the benefit from pipelining or impose unrealistic buffer requirements. In this paper, a high-performance improved reduction method is proposed and analyzed for FPGA platform. This design runs in optimal time while requires only four buffers of fixed size and a single pipelined floating-point unit. Using ALTERA Cyclone II EP2C70F896C6 as the target device, we implement vector summation which is most common example of vector-reduction using improved reduction method.