DocumentCode
552318
Title
CMOS low-dropout regulator with improved time response
Author
Blakiewicz, Grzegorz
Author_Institution
Dept. of Microelectron. Syst., Gdansk Univ. of Technol., Gdansk, Poland
fYear
2011
fDate
16-18 June 2011
Firstpage
279
Lastpage
282
Abstract
A new configuration of CMOS low-dropout (LDO) regulator is presented. In the proposed regulator a low-output-resistance stage with improved time response is used as an output stage. The analysis of basic parameters together with simulation results are provided to characterize properties of the circuit. The comparison of the new configuration and a know structure using flipped voltage follower (FVF) shows over 100% improvement in suppression of the output voltage undershoot.
Keywords
CMOS integrated circuits; integrated circuit modelling; voltage regulators; CMOS low dropout regulator; flipped voltage follower; low output resistance stage; output voltage undershoot; time response; CMOS integrated circuits; Capacitance; Regulators; Resistance; System-on-a-chip; Transistors; Voltage control; CMOS technology; LDO regulator; low-voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 Proceedings of the 18th International Conference
Conference_Location
Gliwice
Print_ISBN
978-1-4577-0304-1
Type
conf
Filename
6015924
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