• DocumentCode
    55683
  • Title

    A LDO Regulator With Weighted Current Feedback Technique for 0.47 nF–10 nF Capacitive Load

  • Author

    Xiao Liang Tan ; Sau Siong Chong ; Pak Kwong Chan ; Dasgupta, Uday

  • Author_Institution
    Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore
  • Volume
    49
  • Issue
    11
  • fYear
    2014
  • fDate
    Nov. 2014
  • Firstpage
    2658
  • Lastpage
    2672
  • Abstract
    A Weighted Current Feedback (WCF) technique for output capacitorless low-dropout (OCL-LDO) regulator is presented in this paper. Through feedback of a weighted current, the WCF permits smart management of the output impedance as well as the gain from the inter-gain stage. Based on the Routh-Hurwitz stability criterion, the WCF can avoid the right-half plane (RHP) pole and push the left-half plane (LHP) non-dominant complex pole pair to a higher frequency. Besides, it provides good regulator loop gain and fast transient response. Validated by UMC 65 nm CMOS process, the simulation and measurement results have shown that the WCF LDO regulator can operate at a load capacitance (CL) range from 470 pF to 10 nF with only 3.8 pF compensation capacitor. At a supply of 0.75 V and a quiescent current of 15.9 μA, the proposed circuit can support a maximum load current (IL) of 50 mA. When IL switches from 0 to 50 mA in 100 ns, the output can settle within 400 ns for the whole CL range. For a case of single capacitor (CL 470 pF), the settling time is only 250 ns. The comparison results have shown that the WCF LDO regulator offers a comparable or better transient figure-of-merit (FOM) and additional merit to drive wide load capacitance range.
  • Keywords
    CMOS integrated circuits; Routh methods; capacitance; circuit feedback; low-power electronics; voltage regulators; FOM; LHP nondominant complex pole pair; OCL-LDO regulator; RHP pole; Routh-Hurwitz stability criterion; UMC 65 nm CMOS process; WCF LDO regulator; WCF technique; capacitance 3.8 pF; capacitance 470 pF to 10 nF; current 0 mA to 50 mA; current 15.9 muA; fast transient response; intergain stage; left-half plane nondominant complex pole pair; output capacitorless low-dropout regulator; output impedance; regulator loop gain; right-half plane pole; size 65 nm; time 100 ns; time 250 ns; time 400 ns; transient figure-of-merit; voltage 0.75 V; weighted current feedback technique; wide load capacitance range; Capacitors; Circuit stability; Impedance; Regulators; Stability criteria; Topology; Cascode compensation; LDO regulator; Miller compensation; weighted current feedback (WCF); wide load capacitance range;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.2014.2346762
  • Filename
    6891377