Microelectronics neural bridge IC with voltage stimulation

Author

Wenyuan, Li ; Fei, Pei

Author_Institution

Inst. of RF - & OE-ICs, Southeast Univ., Nanjing, China

Volume

2

fYear

2011

fDate

15-17 Oct. 2011

Firstpage

1139

Lastpage

1143

Abstract

A microelectronics neural bridge IC with voltage stimulation designed in CSMC 0.5μm CMOS process is presented. This IC is expected to be used for bridging animal´s spinal nerves or peripheral nerves. It is composed of a neural electrical signal detecting circuit, a signal amplifying circuit, a DC offset compensating circuit and a functional electrical stimulation (FES) circuit. Two high performance op-amps are designed in the microelectronics neural bridge IC: a low noise op-amp and a constant-transconductance (constant-g_m) rail-to-rail input/output op-amp. According to the neural signal spectrum, the bandwidth of the IC is designed from 400 Hz to 4 kHz. The chip area is 1050μm×850μm. The power consumption is 914μA when the supply voltage is ± 2.5V.

Keywords

CMOS integrated circuits; bridge circuits; low noise amplifiers; operational amplifiers; signal detection; CSMC CMOS process; DC offset compensating circuit; animal spinal nerves; constant-transconductance; current 914 muA; frequency 400 Hz to 4 kHz; functional electrical stimulation circuit; low noise op-amp; microelectronics neural bridge integrated circuit; neural electrical signal detecting circuit; peripheral nerves; rail-to-rail input/output op-amp; signal amplifying circuit; size 0.5 mum; voltage stimulation; Bridge circuits; CMOS integrated circuits; Capacitors; Microelectronics; Noise; Transistors; CMOS; constant-gm; neural signal; op-amp; rail-to-rail;

fLanguage

English

Publisher

ieee

Conference_Titel

Biomedical Engineering and Informatics (BMEI), 2011 4th International Conference on

Conference_Location

Shanghai

Print_ISBN

978-1-4244-9351-7

Type

conf

DOI

10.1109/BMEI.2011.6098377

Filename

6098377