An implementation of a real-time and parallel processing ECG features extraction algorithm in a Field Programmable Gate Array (FPGA)

Author

Hu, Weichih ; Lin, Chun Cheng ; Shyu, Liang Yu

Author_Institution

Dept. of Biomed. Eng., Chung Yuan Christian Univ., Chungli, Taiwan

fYear

2011

fDate

18-21 Sept. 2011

Firstpage

801

Lastpage

804

Abstract

The objective of the paper is to report a development of real-time and parallel processing algorithm to implement it into a Field Programmable Gate Array (FPGA) for the electrocardiogram (ECG) signals feature extraction. The prototyped system will be extracting the ECG features and tested as a System on Chip (Soc) design. The performance of algorithm was tested against MATLAB routine and validated results based on the MIT-BIH Arrhythmia database which has been annotated by cardiologists. The ECG signals from five volunteers were acquired, tested, analyzed and displayed in on line. This overall detection tolerance of the algorithm was 0.01 seconds.

Keywords

electrocardiography; feature extraction; field programmable gate arrays; integrated circuit design; integrated circuit testing; medical signal processing; parallel processing; real-time systems; system-on-chip; ECG features extraction algorithm; ECG signals feature extraction; FPGA; MATLAB routine; MIT-BIH arrhythmia database; SoC design; cardiologists; electrocardiogram signals feature extraction; field programmable gate array; overall detection tolerance; parallel processing algorithm; prototyped system; real-time processing algorithm; system on chip design; Electrocardiography; Feature extraction; Field programmable gate arrays; Heart beat; MATLAB; Real time systems; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computing in Cardiology, 2011

Conference_Location

Hangzhou

ISSN

0276-6547

Print_ISBN

978-1-4577-0612-7

Type

conf

Filename

6164687