Hardware implementation of a modified randomized cryptographic algorithm

This paper presents a modified randomized cryptographic algorithm for secure exchange of secret keys. The existing randomized cryptographic algorithm (RCA) uses a dibit as the reference bits for encrypting the data of different sizes. However for large data sizes, this procedure takes more operations for the generation of key. The novelty of our work is to use a variable reference bit size that reduces the number of operations thereby making efficient resource utilization. The hardware used to realize the proposed modified randomized cryptographic algorithm (MRCA) is therefore made area efficient. The proposed MRCA is implemented using Verilog HDL and simulated using ModelSim. Synthesis results obtained using Synopsys design vision tool with UMC180 nm technology reveals that there is a 44% reduction in area and 45% dynamic power savings in the proposed MRCA when compared with the existing RCA. The layout of the proposed MRCA is implemented using Cadence SoC encounter and the report summary is generated.