• DocumentCode
    562966
  • Title

    Design of lowpower ALU using 8T FA and PTL BasedMUX circuits

  • Author

    Nehru, K. ; Shanmugam, A. ; Darmilathenmozhi, G.

  • Author_Institution
    ECE Dept., Bannari Amman Inst. of Technol., Sathyamangalam, India
  • fYear
    2012
  • fDate
    30-31 March 2012
  • Firstpage
    724
  • Lastpage
    730
  • Abstract
    In this paper we proposed an ALU using Novel 8T full adder and Pass transistor logic based multiplexers. A 4×1 and a 2×1 multiplexer were used to design an ALU. Full adder is an essential component for designing all types of processors like digital signal processors (DSP), microprocessors etc. In existing method full adder and multiplexers were designed using transmission gate logic. To reduce the number of transistors multiplexers were designed using pass transistor logic and the full adder is designed using 8 transistors. Full adder is designed using 8 transistor logic and multiplexers were designed using pass transistor logic and this is used in the implementation of ALU. In the implementation of ALU, the power and the area were greatly reduced to more than 70% compared to the existing method.
  • Keywords
    Digital signal processing; Digital signal processors; Multiplexing; Reliability engineering; Silicon; Very large scale integration; 8TFA; Pass transistor logic; Transmission gate;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Advances in Engineering, Science and Management (ICAESM), 2012 International Conference on
  • Conference_Location
    Nagapattinam, Tamil Nadu, India
  • Print_ISBN
    978-1-4673-0213-5
  • Type

    conf

  • Filename
    6216200