3D floorplanning considering vertically aligned rectilinear modules using T∗-tree

Three-dimensional integrated circuits gain more and more attention due to their benefits in wirelength reduction and their potential for heterogeneous integration of systems on a chip. Besides the advantages they also lead to new challenges and increasing complexity in designing such systems. This paper focuses on floorplanning such systems. It describes a new data structure called T*-tree which enables the design of three-dimensional integrated circuits considering vertically aligned rectilinear 2D modules. The problem formulation of the new T*-tree differs from the T-tree proposed in [1]. Furthermore, an optimization algorithm is presented which is aware of fixed-outline constraints using a longest path based method. Experimental results show that the T*-tree is competitive to other approaches. It is also able to consider more appropriate modules for three-dimensional integration.