Circuit-level design technique to mitigate impact of process, voltage and temperature variations in complementary metal-oxide semiconductor full adder cells

Modern digital circuits are facing aggressive technology and voltage scaling under emerging technology generations. This study proposes a circuit-level technique to mitigate the adverse effects of process, voltage and temperature (PVT) variations on the design metrics of full adder (FA) cells under such ultra-deep sub-micron technology nodes. The proposed FA cells exhibit improved variability because of the use of inverting low voltage Schmitt trigger sub-circuits incorporated in the designs in place of inverters. The proposed circuits have been designed to operate in the near-threshold region, which offers a trade-off between performance and power consumption. The comparative analysis based on Monte Carlo simulations in a SPICE environment, using the 16-nm complementary metal-oxide semiconductor predictive technology model, demonstrates that the proposed technique is capable of mitigating the impact of PVT variations on major design metrics such as power, delay and power-delay product in FA cells. This improvement is achieved at the expense of two extra transistors for every replaced inverter in the FA cell.