Noble Failure Analysis procedure for trench MOSFET technology devices through detail electrical parameter characterization and unique Fault Isolation technique

The demand for exponential improvement in MOSFET performance versus cost has driven the Industry to miniaturize the die size thus maximizing the die density per square inch of wafer, and exploring breakthroughs in the device design and the wafer fabrication processes. The conventional planar Gate structure on top of the silicon surface is now being replaced by vertical gate micro structure inside hundreds of trenches in the silicon itself. The smaller pitch between the Gates, the deeper Polysilicon Gate and the thinner Gate Oxide in the trenches demand new and improved procedure for Failure Analysis technique of such devices. The paper describes the detail of the electrical parameter characterization to determine the location of the defect in the structure, the unique Fault Isolation technique to identify the exact defect location, and the noble failure analysis technique to uncover the defect and the failure mechanism causing the specific electrical failure mode of the device. Electrical parameter characterization of the Leakage and the VTH parameters, Fault isolation technique using Backside and Topside PEM/OBIRCH, FIB circuit stitching procedure, and the progressive FIB/TEM technique are discussed.