• DocumentCode
    573610
  • Title

    On the functional test of L2 caches

  • Author

    Riga, M. ; Sanchez, E. ; Reorda, M. Sonza

  • Author_Institution
    Dipt. di Autom. e Inf., Politec. di Torino, Turino, Italy
  • fYear
    2012
  • fDate
    27-29 June 2012
  • Firstpage
    84
  • Lastpage
    90
  • Abstract
    Caches are crucial components in today´s processors (both stand-alone or integrated into SoCs) and they account for a growing percentage of the occupied silicon area. Therefore, their test (both at the end of the manufacturing and on-line) is crucial for the quality and reliability of the whole product. While in many cases cache test is based on Design for Testability (DfT) techniques, there are situations in which the functional approach is the only viable one. Previous papers addressed the issue of developing test programs for testing caches: since the constant trend is to organize them in different levels, in this paper we address the test of second level caches (L2). To the best of our knowledge, the paper presents the first functional test method for L2 caches: some experimental results also are provided to assess its effectiveness on the OpenSPARC T1 processor.
  • Keywords
    cache storage; design for testability; integrated circuit reliability; integrated circuit testing; DfT techniques; L2 cache functional test approach; OpenSPARC T1 processor; design for testability techniques; reliability; second level cache testing; silicon area; Design for testability; Manufacturing; Program processors; Reliability; Silicon; System-on-a-chip; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    On-Line Testing Symposium (IOLTS), 2012 IEEE 18th International
  • Conference_Location
    Sitges
  • Print_ISBN
    978-1-4673-2082-5
  • Type

    conf

  • DOI
    10.1109/IOLTS.2012.6313846
  • Filename
    6313846