Thread-level redundancy fault tolerant CMP based on relaxed input replication

To obtain the benefit of aggressive CMOS scaling, chip multiprocessors (CMP) has the tendency of integrating more processors on one chip. However, the increase of cores and voltage factors are increasing susceptibility of CMP to transient faults, hard errors, and process variations. This challenge makes thread-level redundancy (TLR) more attractive in fault tolerance. The proposed CMP architecture executes two copies of a thread on separate cores, so one hard error cannot influence both threads simultaneously. Redundant threads maintain identical hardware resources and independent memory operations. The committed store can update L1 cache before verification. Because updating the unverified values to L2 cache is not allowed, redundant threads do not suffer the non-determinism in parallel applications. Added cache architecture is proposed to buffer thousands of unverified instructions; consequently long latencies in verification can be tolerated. The experimental results show that, for several parallel applications from the SPLASH-2, the performance loss incurred is only 3% due to redundancy.