Hierarchical control flow matching for source-level simulation of embedded software

Source-level simulation (SLS) of embedded software annotates the source code based on the matching of the control flow graphs (CFG) between the source code and the cross-compiled binary code. However, existing SLS approaches still can not guarantee to find a matching for a CFG that is optimized by the compiler. Further, they rely on debug information, which may be unreliable. In this paper, the authors propose a hierarchical CFG matching approach to reduce the influence of compiler optimization and ambiguous debug information. This approach divides the CFGs of the source and binary code into nested regions. Then the matching of those two CFGs is performed for the regions in a top-down manner. In this way, heavy optimization or debug misinformation of certain basic blocks will not have global impact on the matching of other basic blocks. Moreover, optimized loops and branches are matched with respect to the optimization techniques used by the compiler.