FPGA implementation and evaluation of discrete-time chaotic generators circuits

In this paper, implementation of discrete-time chaotic generators widely used in digital communications is studied and evaluated. The study focuses on power consumption, resource usage, and maximum execution frequency of implementations for two common Field Programmable Gate Arrays (FPGAs). While the Bernoulli map ranks first in all three aspects, results show significant ranking differences among the other chaotic generators. Results were obtained by first implementing the chaotic generators in a high level register to transistor level description language and then using tools from FPGA manufacturers to obtain the resource usage as well as estimate the other desired characteristics.