• DocumentCode
    584259
  • Title

    Multi-level EDT to Reduce Scan Channels in SoC Designs

  • Author

    Li, Guoliang ; Qian, Jun ; Li, Peter ; Zuo, Greg

  • Author_Institution
    Adv. Micro Devices, Shanghai, China
  • fYear
    2012
  • fDate
    19-22 Nov. 2012
  • Firstpage
    77
  • Lastpage
    82
  • Abstract
    This paper presents a new multi-level EDT scheme to reduce scan channels of scan-based SoC designs. Multi-level EDT requires trivial modification on existing EDT scheme with two-pass encoding. Experimental results show that this scheme can reduce channel count by up to 30% without penalty of test coverage and pattern count.
  • Keywords
    system-on-chip; channel count; embedded deterministic test; multilevel EDT scheme; scan based SoC design; scan channels; two pass encoding; Benchmark testing; Clocks; Encoding; Equations; Phase shifters; Ring generators; System-on-a-chip; Embedded Deterministic Test (EDT); multi-level EDT; reduce scan channels; scan-based testing; test data compression;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium (ATS), 2012 IEEE 21st Asian
  • Conference_Location
    Niigata
  • ISSN
    1081-7735
  • Print_ISBN
    978-1-4673-4555-2
  • Electronic_ISBN
    1081-7735
  • Type

    conf

  • DOI
    10.1109/ATS.2012.70
  • Filename
    6394179
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=584259