Multi-Clock DFT architecture for interface characterization and power

To address timing closure, interface characterization and power problems during test, a DFT architecture is presented for Multi-Clock designs. Results show that interface characterization is now able to be completed with ATPG, that test power is programmable, and that ATPG capture clock timing is unneeded. Current implementations include 65nm and 40nm Multi-Media Compression IC´s consisting of 18 to 46 clock domains, four to eight PLL´s, and several external interfaces.