Synthesizable delay line architectures for digitally controlled voltage regulators

This paper introduces a new architecture for a fully synthesizable digital delay line (DDL) used in digitally controlled voltage regulators. The new architecture uses a variable number of delay elements to lock to the clock frequency depending on the actual process corner and the temperature variations. Also, a comparison between the proposed scheme and the conventional delay line with discretely programmable delay cells is presented. Both schemes are designed using a hardware description language (HDL) and synthesized using Intel 32 nm technology. The comparison shows that the proposed architecture has better linearity, area, and a fast calibration time with respect to conventional delay lines.