Radiation hardened 2Mbit SRAM in 180nm CMOS technology

Author

Arbat, A. ; Calligaro, C. ; Roizin, Y. ; Nahmad, D.

Author_Institution

RedCat Devices srl Co., Milan, Italy

fYear

2012

fDate

2-5 Oct. 2012

Firstpage

1

Lastpage

5

Abstract

This work presents an asynchronous 2Mbit SRAM designed following radiation hardening by design methodology. The design takes into account the two possible effects that could damage the circuits in harsh environments: cumulative effects due to long-time exposure to radiation and single event effects due to interaction with charged particles. The circuit has been fabricated in an 180nm TowerJazz CMOS process. Post-irradiation measurements of a previous design using the same design methodology confirm that the SRAM is rad-hard up to 760krad of Total Ionizing Dose (TID) for a 100rad/s dose rate.

Keywords

CMOS memory circuits; SRAM chips; asynchronous circuits; integrated circuit design; radiation hardening (electronics); CMOS technology; TowerJazz CMOS process; asynchronous SRAM; cumulative effects; design methodology; post-irradiation measurements; radiation hardened SRAM; single event effects; size 180 nm; storage capacity 2 Mbit; total ionizing dose; CMOS integrated circuits; CMOS technology; Computer architecture; Radiation hardening; Random access memory; Standards; Transistors; Radiation Hardening-by-design; SRAM; Semiconductor memory; Total Ionizing Dose;

fLanguage

English

Publisher

ieee

Conference_Titel

Satellite Telecommunications (ESTEL), 2012 IEEE First AESS European Conference on

Conference_Location

Rome

Print_ISBN

978-1-4673-4687-0

Electronic_ISBN

978-1-4673-4686-3

Type

conf

DOI

10.1109/ESTEL.2012.6400164

Filename

6400164