Methodology for fault grading high speed I/O interfaces used in complex Graphics Processing Unit

Author

Khare, Ashish ; Kishore, P. ; Reddy, Swetha ; Rajan, K. ; Sanghani, A.

Author_Institution

Nvidia Graphics, Bangalore, India

fYear

2012

fDate

5-8 Nov. 2012

Firstpage

1

Lastpage

8

Abstract

Graphics Processing Unit (GPU) requires I/O bandwidth of the order of Gbps which can be met by implementation of High Speed Serializer/Deserializer differential I/Os with clock embedded in data stream, traditionally tested using functional Built In Self Test (BIST). Implementation of these I/Os on complex graphics chip poses requirement for fault grading these I/Os. This paper presents the challenges involved in fault grading SerDes I/Os used in Nvidia´s GPU chips and proposes methodology for extracting fault coverage numbers using industry standard tools.

Keywords

built-in self test; clocks; fault diagnosis; graphics processing units; integrated circuit testing; BIST; GPU; Nvidia GPU chips; clock; complex graphics chip; complex graphics processing unit; data stream; deserializer differential I/O; fault coverage number extraction; fault grading SerDes I/O; fault grading high speed I/O interfaces; functional built-in self-test; high speed serializer I/O; industry standard tools; Built-in self-test; Circuit faults; Graphics processing units; Industries; Receivers; Standards; Transmitters;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference (ITC), 2012 IEEE International

Conference_Location

Anaheim, CA

ISSN

1089-3539

Print_ISBN

978-1-4673-1594-4

Type

conf

DOI

10.1109/TEST.2012.6401585

Filename

6401585