Cell-to-cell interference compensation schemes using reduced symbol pattern of interfering cells for MLC NAND flash memory

Cell-to-cell interference compensation schemes using reduced symbol pattern of interfering cells for multi-level cell (MLC) NAND flash memory are proposed in this paper. The proposed schemes contain three signal-processing techniques, estimating cell-to-cell interference, compensating cell-to-cell interference, and generating log-likelihood ratio (LLR). Firstly, reduced symbol pattern of interfering cells is used to easily estimate cell-to-cell interference by setting threshold voltage shift to be only two values in the programming state. Based on this estimation, cell-to-cell interference is compensated by modifying the read voltage in the proposed scheme 1 and by subtracting the estimated cell-to-cell interference from the sensed voltage in the proposed scheme 2. Finally, after conducting compensation, LLR is calculated for low-density parity check codes in the assumption of free cell-to-cell interference since interference between cells is mitigated by the compensation procedure. By using these techniques, the interference can be relaxed with a simpler structure and a higher reliability compared to the conventional methods for MLC NAND flash memory.