A low power ASIP for precision configurable FFT processing

Fast Fourier transformation (FFT) is a key operation in digital communication systems. Different communication standards require various FFT length and precision. In this paper, we present a low power Application-Specific Instruction-set Processor (ASIP) for variable length (16-point-4096-point) and bit precision (8-bit - 16-bit) to meet different requirements. We use scalable multipliers to construct the butterfly unit, which support both 8-bit and16-bit operation. The order of butterfly operation is adjusted to reduce twiddle-factorROM accesses, so as to reduce overall power consumption efficiently. Clock Gating is implemented to shut down processor´s pipeline during the FFT processin terms of special low power demands. Special Instructions are tailored to make full use of the flexible hardware.