Performance optimization of high-speed Interconnect Serial RapidIO for onboard processing

Serial RapidIO is a high-performance, packet-switched that was developed to address the embedded industry´s need in term of faster bus speeds, increased bandwidth and reliability. Serial RapidIO allows chip-to-chip and onboard communications. In this paper, we present experimental results on performances optimizations of the Serial RapidIO interconnect integrated in the new digital signal processor (DSP) multi-core TMS320C6474. Our results show that the two transactions Nwrite and Swrite achieve more performances and we determine that in order to transfer a data stream, the interrupt method is the simplest and it increases transfer robustness. The performance difference between the interrupt method and method of EDMA in synchronized mode is tolerable.