Delay model for VLSI RLCG global interconnects line

Due to high packaging density of components, delay modelling is increasingly becoming the bottleneck for the design of high performance VLSI circuits. At higher frequency of operations, of the order of few GHz, the on-chip interconnect is to be analyzed with a distributed RLCG model. Because at very high frequency, the dielectric material deviates from its ideal nature. This gives rise to the shunt conductance matrices. The Elmore delay can deviate for typical RLCG interconnections with ramp input from SPICE computed delay. Since it is independent of rise time of the input ramp signal. In the performance driven synthesis and design of VLSI routing topologies Elmore delay is widely used as an analytical model of interconnect delay. We develop a new analytical delay model based on the first and second moments of the interconnect transfer function when the input is a ramp signal with finite rise time. The simulation results justify the efficacy of the proposed delay estimation model.