A fully complementary and fully differential self-biased asynchronous CMOS comparator

This paper presents a novel CMOS asynchronous voltage comparator topology composed of a preamplifier cascaded by the positive feedback latch. The proposed circuit is fully differential and possesses desired properties like purely capacitive input impedance with rail-to-rail output swing, low noise and offset, etc. Furthermore, the comparator is also completely self-biased embedding the negative feedback in the biasing loop which makes it highly resistant to process, supply voltage and temperature variations. The design and optimization methodologies are discussed as well. Since the comparator delivers high operating speeds under relatively low power consumption, it is suitable for use in tomorrow´s SoC data transceivers and converters.