Maximum delay variation temperature-aware standard cell design

Standard cell design suffers from temperature-induced delay uncertainty. In this paper we propose two methodologies to cope with this issue before the logic synthesis step without modifying the standard flow. Both methodologies are based on the study of the cell maximum delay sensitivity to temperature variations to select the cells of the library to be used for the synthesis. We provide icyflex2 CSEM processor synthesis to demonstrate the delay variability reduction obtained.