Process optimization for random threshold voltage variation reduction in nanoscale MOSFET by 3D simulation

Author

Hui Li ; Hao Chen ; Qing Dong ; Lele Chen ; Jianping Wang ; Jeonggi Kim ; Shaofeng Yu ; Jingang Wu ; Yinyin Lin

Author_Institution

ASIC & Syst. State Key Lab., Fudan Univ., Shanghai, China

fYear

2012

fDate

Oct. 29 2012-Nov. 1 2012

Firstpage

1

Lastpage

3

Abstract

Process optimization strategy to reduce random threshold voltage (Vt) variation for CMOS at 65 nm and beyond is presented. The impact of related process parameters such as halo/Vt implant species, energy and dosage on Vt mismatch are analyzed and compared by 3D TCAD simulation. It is revealed that the random dopant fluctuation (RDF) can be dramatically suppressed by carbon implant with sufficient dosage combines proper energy. Besides, Vt tuning and halo implants by indium is recommended because it is less susceptible to Vt variation than Bf2. All these results of process optimization can be well explained by the shift of impurity doping level near the surface.

Keywords

CMOS integrated circuits; MOSFET; technology CAD (electronics); 3D TCAD simulation; 3D simulation; RDF; halo-Vt implant species; nanoscale MOSFET; process optimization; random dopant fluctuation; random threshold voltage variation reduction; size 65 nm; Carbon; Implants; Impurities; Indium; Optimization; Resource description framework; Tuning;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on

Conference_Location

Xi´an

Print_ISBN

978-1-4673-2474-8

Type

conf

DOI

10.1109/ICSICT.2012.6467853

Filename

6467853