Research on high speed mixed-signal SoC verification based on NanoSim-VCS with a 4.8Gb/s SerDes transmitter

With the rapid development of semiconductor manufacturing technology, more and more analog and mixed-signal blocks are integrated into system-on-chip. In order to guarantee the products yield, complex full chip system verification before tape-out has been a bottle-neck in mixed-signal system design. This paper proposes a verification method for large mixed-signal SoC designs using Synopsys Discovery AMS platform based on NanoSim-VCS, which is used to verify TSH300, a 4.8Gbps 5+1-lane SerDes transmitter system in TSMC 65nm CMOS including both digital and analog modules. This method provides simulation with high accuracy and speed, especially much faster than traditional method in speed. The simulation time using this method is only about 15% of the period of the simulation based on traditional method. The feasibility and efficiency of this method has been verified in tape-out.