A new 6-transistor SRAM cell for low power cache design

Power consumption is becoming a pressing issue in cache design. And SRAM (static random access memory) cells occupy a large area of the cache. Recent research shows that SRAM´s power dissipation contributes to a key part of the whole chip power consumption. By using separate write and read operation, this paper presents a new 6T-SRAM cell structure of nano-scale technology for low power application. Simulation results with standard 65nm CMOS (complementary metal oxide semiconductor) technology show that the speed is closed to the traditional 6T cell, power consumption is reduced by 22.45% during the write operation of 0. Particularly, in idle mode this structure maintains its data with the help of leakage current and positive feedback, which can greatly improves the power consumption of the nano-scale SRAM.