Design and implementation of Carry Select Adder without using multiplexers

High performance digital adder with reduced area and low power consumption is an important design constraint for advanced processors. The speed of operation of such an adder is limited by carry propagation from input to output. Our work is based on designing an optimized adder for advanced processors. This paper discusses about the implementation of Carry Select Adder without using MUX for final selection. Our approach uses first, the implementation of cin=0 adder and then Excess 1 adder. Excess 1 adder is designed in such a way that it becomes a first zero finding logic and replaces the final MUX stage used in traditional approach. Parallel adder configuration is also used to reduce the delay between stages. Removing the MUX stage will reduce the area as well as propagation delay to give much higher performance for the adder. The Kogge Stone parallel approach will give option to generate fast carry for intermediate stages. The adder is implemented on Spartan 3E FPGA and is compared with CSA with MUX, Kogge Stone adder and FPGA adder. Results show that the new adder gives reduced area and better speed compared to other adders.