Conducted EMI in SiC JFET inverters due to substrate capacitive coupling

This paper investigates the conducted EMI in SiC JFETs based inverters for motor drives under the influence of capacitive coupling from two types of substrates - Insulated Metal Substrate (IMS) and heat sinks. The inverter prototypes are implemented with the discrete SiC Transistors attached on top of the two substrates, which creates capacitive coupling between the device drain plate and the substrate base plate. The resulting EMC differences are analyzed and compared. It is found that the employment of IMS significantly deteriorates the EMC performance due to the extensive capacitive coupling magnitude. The method of using another substrate layout - each SiC JFET is placed on top of a separated heat sink to minimize the coupling is proposed. The EMI spectrums of the above inverters are compared under unfiltered and filtered conditions. It is found that the inverter version of using separated heat sinks reduces EMI both in the middle and high frequency ranges, which greatly releases the filtering effort. Finally, their different EMI filter requirements are analyzed and implemented, which effectively suppresses the conducted EMI to comply with the standard prescribed by IEC61800-3 C2 Qp.