A 9b 1GS/s 27mW two-stage pipeline ADC in 45nm SOI-CMOS

A novel, 9b 1GS/s 2-stage pipeline ADC architecture enables high performance with a low-gain op-amp and poor accuracy in the sub-ADC comparators. A reduced MDAC gain of two relaxes the op-amp gain and bandwidth requirements by a factor of 5.7. Deliberate and random comparator mismatch set the trip-points in the 2^nd stage flash sub-converter and decouples performance from matching requirements. Digital trimming of a delay chain eliminates mismatch in the sampling paths to provide a simple, low power alternative to a dedicated front-end SAH. The ADC achieves an ENOB of 7.4b at Nyquist, consumes 27mW from a 1.0V supply, yielding an FOM of 160fJ/conversion-step.