Analysis and Improvement of Transformation-Based Reversible Logic Synthesis

Ultra-low power dissipation for nanoscale circuits and future technologies such as quantum computing require reversible logic. Existing methods of reversible logic synthesis attempt to minimize gate count, quantum cost, garbage count and try to achieve scalability for large Boolean functions. Several notable heuristics for reversible logic synthesis employ a method based on repeated transformation, demonstrating excellent performance compared to available optimal results. In this paper, we suggest two novel techniques to the transformation-based synthesis flow for improving synthesis outcome. The first technique is based on properties of Boolean functions and the second technique incorporates generalized Fredkin gates during synthesis flow. We present theoretical results and experimental evidence in support of our strategies.