Synthesis of Balanced Ternary Reversible Logic Circuit

Author

Mondal, Bikromadittya ; Sarkar, Pradyut ; Saha, Prabir K. ; Chakraborty, Shiladri

Author_Institution

Dept. of Comput. Sci. & Eng., B.P. Poddar Inst. of Manage. & Technol., Kolkata, India

fYear

2013

fDate

22-24 May 2013

Firstpage

334

Lastpage

339

Abstract

Ternary logic synthesis has a significant role to realize multi-input ternary logic functions. Balanced ternary logic that contains three states as -1, 0 and 1 has substantial advantage over standard ternary logic containing the logic states as 0, 1 and 2. The paper addresses the synthesis of balanced ternary reversible logic circuit and design of reversible half-adder and full-adder circuit by using balanced ternary reversible logic gates. We also introduce balanced ternary multiplier gate that is used to design of single trit and multi-trit multiplier circuit. Hardware complexity of each circuit is investigated.

Keywords

logic circuits; logic gates; ternary logic; balanced ternary multiplier gate; balanced ternary reversible logic circuit synthesis; balanced ternary reversible logic gates; hardware complexity; logic states; multiinput ternary logic functions; multitrit multiplier circuit design; reversible full-adder circuit design; reversible half-adder circuit design; single trit multiplier circuit design; Adders; Clocks; Logic circuits; Logic gates; Multivalued logic; Quantum computing; Vectors; Balanced ternary logic; Full-adder; Half-adder; Multiplier; Reversible logic gate;

fLanguage

English

Publisher

ieee

Conference_Titel

Multiple-Valued Logic (ISMVL), 2013 IEEE 43rd International Symposium on

Conference_Location

Toyama

ISSN

0195-623X

Print_ISBN

978-1-4673-6067-8

Electronic_ISBN

0195-623X

Type

conf

DOI

10.1109/ISMVL.2013.53

Filename

6524686