Modeling of NBTI-recovery effects in analog CMOS circuits

In addition to the well-known longtime degradation of CMOS circuits by Bias Temperature Instability (BTI) degradation, short stress pulses and subsequent recovery of parameter shifts can cause inaccurate transient response in CMOS circuits. Aging simulations to detect such failures in analog circuits like comparators and analog-to-digital converters require implementation of an analytic BTI model, as ΔV_th-shifts and recovery effects have to be analyzed in every simulation time step. Therefore, we developed a simulation model for NBTI degradation including its recovery effects and an implementation of this NBTI model in a SPICE environment. With this toolset, a fast characterization of different circuit topologies is possible. The simulation model covers both DC- and AC-stress. The model is applied to analyze a comparator in switched-capacitor technique. In spite of offset compensation by auto-zeroing, it shows erroneous behavior due to the fast recovering part of the ΔV_th shift.