A physics-based compact model for SCR devices used in ESD protection circuits

A CMOS SCR compact model is developed for circuit simulation of ESD protection circuits. The model is comprised of coupled NPN and PNP transistors. A previously unnoted interaction between these transistors is described, resulting in improved agreement between simulation and measurement. This model addresses fundamental limitations of previous models, allowing for improved simulation accuracy, while limiting the number of parameters. The model parameters are scalable with respect to the layout spacings.