Erratic bits classification for efficient repair strategies in automotive embedded flash memories

The automotive environment is particularly challenging in terms of requested reliability for electronic components. Flash memories commonly exploited in this framework are subject to this paradigm as well. In semiconductor memories erratic bits are infamously known as a major reliability threat to be handled by repair strategies which spans from static redundancy to dynamic correction codes. Both resources are limited in their amount and correction strength, therefore their usage must be properly tailored. In this work we propose a signature classification methodology for erratic bits that will help the choice of the best repair strategy for each bit, reducing when possible the usage of unnecessary correction resources. This methodology will also turn into a decrease of the chip error probability as demonstrated by an accurate modeling procedure.