Experimental analyses of the mechanical reliability of advanced BEOL/fBEOL stacks regarding CPI loading

The introduction of fragile ultralow-k materials as interlayer dielectrics in backend-of-line interconnect stacks asks for a thorough analysis of potential risks due to chip-package interaction. This paper shows how the application of several ex-situ and in-situ experimental approaches can be effectively used to assess such risks on the wafer level already at early stages of the development phase. The respective analytical techniques try to mimic chip-package interaction loading conditions. Most of the tests transfer loads to interconnect stacks via individual copper pillars. The investigations take place on the scale of about 100μm down to 1μm.